Select Committee on Science and Technology Second Report



4.1  At the heart of every computing device is one or more chips that do the actual computing. This Chapter describes the ways CMOS chips are made and the plans for continuing into the future the miniaturisation achieved over the last 40 years. However, limits to CMOS miniaturisation seem likely to be reached in about 10-15 years. The already sophisticated CMOS technology will then be an even more powerful tool.

4.2  Nevertheless, there may be alternative technologies which can outperform CMOS, even at that level of refinement. Whatever the chip technology, it will be enabled only by advances in some generic manufacturing technologies, as considered at the end of the Chapter. The implications of all this (and the related design matters considered in Chapter 5) for the UK research effort are discussed in Chapter 8.

How a chip is made

4.3  The starting point in the long and complicated chip manufacturing process is a slice of crystalline silicon. Silicon is, after oxygen, the most abundant element on Earth but is found almost wholly in compounds[23] which are also tainted with impurities.

4.4  Pure silicon is obtained from source material by a series of chemical treatments. Together with a small amount of material to give the desired semiconducting properties, it is then melted and carefully cooled (so that the individual atoms settle into a regular crystal lattice) in cylindrical ingots. When cool, the ingot is sliced into circular wafers less than 1 mm thick. Each wafer is then polished to a near-perfect smoothness.

4.5  Nowadays, ingots (and thus the wafers sliced from them) have a diameter of up to 300 mm. As each wafer yields multiple individual chips, larger starting wafers enable more chips to be made at a time, thus reducing the unit cost. CPUs are among the largest chips made. Although now containing over 40 million transistors, they are only about 15 mm square[24], and a 300 mm wafer would yield about 200 such chips. Other chips can be much smaller, enabling several thousand to be fabricated per wafer.

4.6  The manufacture (or fabrication[25]) of chips on a wafer involves about 20 steps — as described in Box 3 — to build up the layers which form the individual transistors and their interconnections. If the resulting chips are to work properly, each of these stages needs to be completed to a very high degree of accuracy. A tiny error in repositioning[26] a wafer for stepping under a mask pattern could wreck a whole wafer. One speck of dust or minor impurity in the materials could render one or more components ineffective and thus ruin at least one of the wafer's multiple chips.

4.7  The completed wafer is stepped under a set of computerised probes that test whether each chip works properly — as discussed in paragraph 5.23. A machine then dices the wafer into the individual chips, discarding the non-working ones. Manufacturing standards are so high that reject rates are generally well below 20%.

4.8  Each good chip is mounted on a packaging unit incorporating an array of pins or legs for connection to the computer's circuit board. In most cases, a wire bonder then links the contact pins with the electrical contacts round the edge of the chip, although newer packaging technologies are emerging. With the addition of a protective cover over the wired-up chip, the unit is then complete.

CMOS technology

4.9  The first chips based on field-effect transistors were made using either all n-type or all p-type transistors[27]. Because the fabrication used Metal, Oxide and Semiconductor, the chip technologies became known as NMOS and PMOS respectively. It was discovered that more efficient designs were possible if chips contained both n-type and the complementary p-type transistors. Although more complicated to fabricate, CMOS (Complementary Metal-Oxide-Semiconductor)[28] has become the dominant technology.

Moore's "Law"

4.10  In a celebrated 1965 article, "Cramming more components onto integrated circuits"[29], Gordon E Moore[30] noted that the number of transistors and other components it was possible to fabricate on a single chip at reasonable cost had doubled every 18 months to two years year since their invention in the late 1950s. He expected this exponential trend to continue for the next 10 years — to 1975.

4.11  This forecast proved remarkably accurate, not only to 1975 but beyond. Box 4 indicates the exponential growth of transistors per chip in Intel's main range. Early on, the press dubbed the trend "Moore's Law" and the name stuck — although it is not, of course, a natural law.

4.12  These figures are illustrated graphically in Box 5. The points are plotted using a logarithmic scale on the vertical axis. Each division on a logarithmic scale is a multiple (in this case, by 10) of the one immediately below. Such a scale enables exponential growth to be plotted as straight line.

The ITRS "roadmap"

4.13  As noted during our visit to NPL[31] and subsequently by others, the chip industry now actively plans ahead to continue the Moore's Law exponential miniaturisation. The umbrella for this planning is the International Technology Roadmap for Semiconductors (ITRS), jointly sponsored by consortia of manufacturers in Europe, Japan, Korea, Taiwan and the US. It reflects massive international consensus between thousands of manufacturing firms.

4.14  Although the United Kingdom has taken some part in the formulation of the ITRS, it is not represented on any of the major committees that form the Roadmap. The Institute of Physics considered this to be a source of great embarrassment and regret (Q 150)[32]. We share the Institute's view that this is indicative of what has happened to the UK semiconductor industry.

4.15  The 2001 ITRS[33] is an extremely detailed document — the Executive Summary alone runs to over 50 pages — covering every conceivable element of CMOS design and manufacture. For each of those elements, the ITRS identifies the year by year improvements (many of which are interdependent) needed to contribute to maintaining the Moore's Law progression. In each case, the Roadmap (a typical table from which is reproduced on the back cover of this Report) identifies whether:

(a)  manufacturable solutions exist and are being optimised;

(b)  manufacturable solutions are known, if not yet implemented (which the ITRS highlights in yellow); and

(c)  manufacturable solutions are not known (which the ITRS highlights in red).

4.16  The point at which there are no known manufacturable solutions to most technical areas has been called the red brick wall, with the aim of concentrating research on the need for breakthroughs in those areas. The 2001 ITRS placed that red brick wall between 2005 and 2007.

The limits to CMOS miniaturisation

4.17  Given past experience, it is reasonable to assume that ways will be found through the 2005-2007 obstacles, but other physical and financial constraints will then come into play.

Physical constraints


4.18  Some of the solutions to those manufacturing obstacles identified as arising in 2005-2007 may be relevant for many years to come. Others may be useful for only a year or so, creating another red brick wall beyond 2007. More R&D would be needed on what will be increasingly challenging problems, with the aim of securing the manufacturing breakthroughs required to maintain the Moore's Law miniaturisation.


4.19  Even if every future manufacturing challenge can be met successfully (which is not certain), a limit set by the fundamental properties of matter is on the horizon. The 2001 ITRS pencilled this in for about 2015.

4.20  CMOS chip technology relies on the well-understood bulk properties of matter. As dimensions diminish, the different properties of individual atoms and electrons come into play. In Dr Cowburn's memorable phrase, "a tenth of a fruit cake is still fruit cake, but a thousandth of a fruit cake is a single currant" (p 80)[34]. The dimensions of individual components on a CMOS chip are already almost unimaginably small. As noted in paragraph 3.13(c), the gate-length of transistors (which limits the maximum speed at which they can be operated) is presently about 100 nm. Some of the layers deposited during fabrication are only 1.5 nm — about 8 atoms[35] — thick.

4.21  Theory indicates that it should be possible to make CMOS transistors with a gate-length of 10-20 nm, in which the active part of the transistor is a body of only a few thousand silicon atoms. Among these would be only a few tens of dopant atoms to give the correct semiconductivity properties, and not more than one or two hundred electrons would be available for conduction in the gate region for the actual switching effect. Below a 10-20 nm gate-length, so few electrons would be involved in the switching function that the need to be able to determine whether or not the switch was on or off would be swamped by the unavoidable uncertainty about the behaviour of individual electrons.

4.22  Although not fundamental in quite the same sense, some barriers are set by heat generation from the electrical power consumed. As transistors get smaller, their switching requires less electrical energy and can be done more quickly. Halving the power consumption per operation but doubling the speed has an overall neutral effect on power consumption per transistor[36]. However, halving the linear dimension of transistors means that four times as many can be fitted in the same area, increasing the maximum power consumption (and the heat generated as a result) per unit area by a factor of four.

4.23  The CPU in a modern PC consumes about 75 watts — about the same as a traditional heated-filament light bulb of medium brightness — in an area of some 200 mm2, or about the size of an adult's thumbnail. This requires fan-assisted cooling to avoid overheating. Significantly greater power consumption per unit area would require chips to be actively refrigerated in some way. Before the fundamental physical limits of CMOS are reached, heat dissipation may mean that chips are run at less that their potential maximum speed.

Financial constraints

4.24  As noted in paragraph 3.15, the first transistors were made singly. This was reflected in the mid-1950s unit price of some US$45. The advent of integrated circuits enabled multiple transistors to be fabricated together, greatly reducing the cost per unit. It is this manufacturing and price efficiency that are the real engine of the Moore's Law progressive miniaturisation. According to the ITRS, the unit price of transistors on the latest chips means that a US dollar would buy more than a million of them. This historic trend (and its projection forward) is illustrated by the chart in Box 6.

4.25  The fact that more densely packed chips can be operated at faster speeds is a bonus. However, the continuing availability of ever greater computing power at lower cost has facilitated the development of new computerised applications. In turn, these have helped expand the market for computing, thus generating the income needed to allow investment in new plant for the fabrication of yet more sophisticated chips.

4.26  The investment required for fabrication is already very substantial. At the time of writing, a state of the art fabrication facility costs about US$2 billion. The investment required coupled with considerations of labour cost has already led to the concentration of chip fabrication in a few centres in the Far East. It seems unrealistic to think that the United Kingdom and others that no longer have state of the art fabrication facilities could break back into the market.

4.27  As Dr Cowburn noted (Q 208), the cost of a chip manufacturing plant about doubles every three years, following a trend that has been called Moore's Second Law. Carrying this trend forward suggests that a single plant to manufacture CMOS chips at their physical limits would cost anything from US$200-500 bn — i.e. about 15-35% of the UK's Gross Domestic Product (GDP)! While it is possible that significantly more cost-effective ways forward might be found, there is a real question whether the investment required for the most advanced CMOS plant could be economically viable.

CMOS at the limits

4.28  For many years, CMOS chips have been climbing the steep part of the business S-curve — see Box 7. As discussed above, the physical limits — and perhaps the earlier financial ones — of CMOS technology are now within sight. The S-curve will flatten out as growth slows and eventually reaches its practical limits. Does this matter?

4.29  Reaching the practical limits of CMOS miniaturisation does not mean that the technology reaches the end of its useful life. CMOS is already a very powerful technology. It will become significantly more so over the coming decade. It will then be a mature, highly sophisticated and relatively cheap technology capable of not only supporting many new and improved applications but also providing scope for many further advances in chip design and architecture (as discussed in Chapter 5).

4.30  After so many years of exponential miniaturisation, the global computing industry will need to find new strategies as CMOS technology reaches maturity. Consumers will no longer be afflicted by the technological obsolescence of the chips in their machines. The new markets seem likely to be for radical new products and applications using (mainly) CMOS technology. For example, the highly innovative remote-sensing wirelessly-networked Smart Dust being developed by CITRIS in California, about which we heard during our visit to Silicon Valley[37], requires little more than today's CMOS technology.

Alternative chip technologies

4.31  If the maturing CMOS chip technology is so good, is there any case for pursuing possible alternative approaches? The answer has to be in the affirmative. We should never be so complacent as to think that there is nothing left to discover. At the same time, it seems unlikely that there will be any obvious crisis which mainstream computer users will be clamouring to have resolved. Moreover, CMOS technology has become dominant for good reason. Because of the massive financial, technical and intellectual investment in this dominant technology, any alternative approaches will need to show promise of quickly becoming very significantly better than CMOS in terms of speed of operation, power efficiency, ease of manufacture (and thus cost) or other functionality.

4.32  For at least the time being, it is hard to see CMOS being simply replaced by some alternative technology. The most likely outcome is that alternatives would show their merits mainly in niche areas and would thus be seen as complementing CMOS rather than being a straight replacement. Against that background, we therefore consider that there is a good case for proportionate investment in research into alternatives to CMOS, as considered further in Chapter 8.

4.33  We have, of course, no way of forecasting where and how worthwhile breakthroughs might be made. However, they seem likely to fall within one or more of the following broad areas.

(a)  Materials. The dominant CMOS chip technology is based on silicon, a semiconducting element in plentiful supply. Other, more exotic, semiconducting elements and compounds are available, some of which may offer improvements over silicon in terms of greater switching speed, lower power consumption or ease of fabrication.

(b)  Medium. Electrical signals might be replaced by much faster optical ones, at least for some interconnections.

(c)  Ultra-miniature devices. As noted in paragraph 4.20, present transistors rely on the bulk properties of matter. It is theoretically possible to construct switching devices from fewer atoms than the minimum needed for CMOS operation. Large molecules of carbon known as carbon nanotubes can demonstrate switching. Switching devices could be made to exploit the magnetic or other properties of individual atoms or even sub-atomic particles. Because such devices could generate only a very weak signal, they may be more useful as ultra-compact memory elements (which have only to register whether they are switched on or off) rather than in a CPU's logic components which have to signal with sufficient strength to drive other parts of the CPU.

(d)  Radical new approaches. Fabrication by conventional means would, to say the least, be problematic at the sub-microscopic size of those ultra-miniature components. Using the developing techniques in nanotechnology, there may be scope for developing means of mechanical self-assembly. Alternatively, biological organisms might be modified to grow into forms which could either provide a template for ultra-miniature computing components or, even more radically, to be the actual computers. Chips are currently made with only one layer of transistors. Self-assembly could facilitate dense packing in three dimensions. Although heat dissipation considerations[38] suggest that the individual components of three-dimensional devices would need to run relatively slowly, that could be offset by the overall gain from such compactness.

(e)  Radical new devices. The preceding possibilities shade into radical new devices which, by definition, may be beyond our present imaginings. At this radical end of the spectrum is quantum computing — see Box 8. The United Kingdom has significant strengths in the theory of quantum computing, recently recognised by the establishment of a Quantum Information Processing Interdisciplinary Research Collaboration, see paragraph 7.19. Fujitsu noted (p 196) that UK strengths could be seen as complementing Japan's strengths in experimental quantum computing. Professor Sir Maurice Wilkes (p 231), however, noted that there are serious doubts about not only the practicality of quantum computing but also its utility for general-purpose applications. If it can be realised, quantum computing would have a major impact in specialised areas such as cryptography.

Generic technologies

4.34  Regardless of how chips are fabricated, other technologies will be also be needed. For the purposes of our Inquiry, the most significant are in the areas of chip design and architecture as discussed in detail in Chapter 5. Other key generic technologies are considered below.


4.35  Unless there are advances in self-assembly (see paragraph 4.33(d)), chip manufacture will continue to require the laying down of almost unimaginably fine patterns in a process known as lithography. The complexity of the present operation (which represents about 40% of the cost of chip manufacture) has been likened[39] to drawing a road map of the whole planet in an area the size of a fingernail. As noted in Box 2, these patterns are projected onto the surface of the chip. However, the minuscule detail required is already beyond the definition which can be achieved with visible light. Ultra-violet (UV) light, which has a shorter wave-length, is used instead.

4.36  Even UV light cannot deliver the precision needed for the projected further miniaturisation of CMOS chip components. The main candidates for meeting this challenge were X-rays, extreme ultra-violet (EUV) light, ion-beams and electron-beams. As we learned during our visit to Silicon Valley[40], EUV has proved the winner.

4.37  The development of the prototype EUV machine took some 10 years while various novel features were perfected. EUV is readily absorbed, so EUV lithography has to be performed in a near vacuum. Instead of shining light through a mask and projecting the reduced image onto the chip through lenses, EUV has to be managed by reflection (requiring special surface materials that absorb very little EUV) off a patterned mirror and via curved mirrors to reduce the image to the required size.

4.38  The work began in some of the publicly-funded US National Laboratories. However, the cost of developing the new technology and the consequent need to ensure that the investment would be recouped led to the establishment of an EUV consortium of all the major companies to share the costs and the rewards. (We were pleased to find that a British company, Exitech Ltd[41], had established a stake in this work in providing state of the art R&D tools.) The prototype EUV lithography machine worked entirely to specification. Work was under way on production machines, planned to meet the lithography requirements of miniaturisation down to the physical limits of CMOS technology.


4.39  Metrology is the science of measurement. Accurate and reproducible measurement of length and thickness is essential at every stage of chip manufacture. Critical linear measurements (for example, in projecting a lithography pattern over a preceding layer) can be as small as 5 nm or 25 atoms.

4.40  DTI funds the National Physical Laboratory so that both the science research base and UK high-technology industry have access to a world-class measurement institute. It is regarded as one of the three leading centres internationally. Nano-scale metrology is an increasingly important element of its activities. During our visit to NPL[42] in March 2002 we saw much high-quality work, including a nano-scale metrology tool (involving a combination of scanning tunnelling microscopy and X-ray interferometry) that had been developed in conjunction with NPL's German counterpart, the PTB. We also noted that, although NPL's expertise was highly relevant to computing technology, its application is not apparently central to the NPL mission, which perhaps explained why the effort was dispersed between several strands of activity.

4.41  When we received oral evidence from the NPL team, we were disappointed to find that, although the Laboratory's expertise had a wide range of potential applications in the future development and manufacture of microprocessors, plans to develop exploitation were still at a relatively early stage (Q 348). NPL argued that much of their expertise was deployed through knowledge transfer to industry (Q 343), but Mr Gower of Exitech Ltd had made more use of the work of the US and German National Measurement Institutes (p 194). His observation that, while NPL had undoubted expertise, it had little profile in the technologies relevant to the semiconductor industry was borne out during our visit to Silicon Valley.

4.42  When we discussed this general matter with the Minister for Science, he agreed the importance of NPL's developing its presence and noted that there was a new three-year strategy in place for this (QQ 489 & 490). Given the vital role of metrology in chip fabrication, we recommend that NPL should urgently complete its review of the way it co-ordinates its activities relevant to microprocessing, and implement a clear strategy for developing and marketing its contribution to the global computing industry.


4.43  Nanotechnology is concerned with the application of material science at or around the nanometre scale. It covers not only processes for working down to the almost sub-microscopically small but also the exploitation of molecules and biological structures to self-assemble tiny structures. The consequent fusion of Physics, Chemistry and Biology holds immense promise across a wide range of potential applications. Some of those applications may be in the field of chip fabrication. In return, many nanotechnology devices will rely on advances in computing. The interplay of these two matters is discussed further in paragraphs 8.8 onwards as part of our more general consideration of ways of strengthening R&D in computing.

23   Some beach sands are mainly silicon dioxide. Back

24   The complexity of a modern chip is illustrated on the front cover of this report. Back

25   In the industry, chip fabrication facilities are known as Fabs. Back

26   Tolerances can be as little as 5 nm - the space occupied by 25 silicon atoms. Back

27   See Box 2. Back

28   Also now expanded into Complementary Metal-Oxide-Silicon. Back

29   Electronics Vol 38 No 8. Back

30   Then Director of Fairchild Semiconductors' R&D Laboratory. He co-founded Intel in 1968. Back

31   See Appendix 4. Back

32   Q refers to a question number in the accompanying volume of evidence. Back

33   Available at Back

34   p refers to a page number in the accompanying volume of evidence. Back

35   Atoms in a silicon crystal are spaced about one fifth of a nanometre apart. Back

36   In reality, the overall power consumption would increase slightly. Insulating properties decline with smaller size so current leakage increases. Back

37   See Appendix 6. Back

38   See paragraphs 4.22 and 4.23. Halving the linear dimension in a three-dimensional structure would increase the maximum power density by a factor of eight. Back

39   "Solid-state Century", Scientific American, special issue 1998. Back

40   See Appendix 6. Back

41   See the company's written evidence on p 194. Back

42   See Appendix 4. Back

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